The present invention relates to a semiconductor memory having a redundancy circuitry and particularly, to a semiconductor memory for which there is applied a designing method to realize a memory capacity (the number of memory bits) which meets a user's desire by increase or decrease in the number of memory segments.
Heretofore, when a memory capacity of a semiconductor memory is changed, there has been a need for a maker to conduct designing of the semiconductor memory from its very start. In recent years, however, there has been arisen a new need for a maker to provide, in a short time period, a semiconductor memory having a memory capacity which meets a user's desire due to product diversification of electronic equipment, increase in complexity of a system and the like. Accordingly, there has been proposed a designing method in which a memory capacity can be changed by increase or decrease in the number of memory segments.
In recent years, attention has also been drawn to the so-called system LSI that a specific system is formed in one chip by integrating a plurality of functions on the one chip. The system LSI is an LSI to gather a plurality of functions, which have respectively been formed in separate chips, on one chip; the system LSI contributes to realization of higher performance, lower power consumption and size reduction (decrease in the number of parts) of a system. In the means time, it is required that there is supplied a semiconductor memory having a memory capacity which meets a user's desire in a short time period in the case of an LSI provided with a function of a semiconductor memory (memory macro) among various system LSIs, for example in the case of a MERGED MEMORY-LOGIC LSI. Hence, for a memory macro in a system LSI as well, there is applied a designing method in which a memory capacity can be changed by increase or decrease in the number of memory segments.
Below described will be a designing method in which a memory capacity can be changed by increase or decrease in the number of memory segments. This designing method employs a circuit block called a memory segment. A memory segment comprises a memory cell array having a specific memory capacity (for example, one megabits), a sense amplifier, a row decoder, a column decoder and the like and is already designed in advance of need. When a semiconductor memory having N megabits, wherein N is a natural number, is designed, N memory segments are used. In this case, each memory segment is not necessary to be redesigned from its start and it is only required that structures of a block decoder and the like are partially changed according to a memory capacity; designing of a semiconductor memory having N megabits can thus be completed in a short time period.
In such a manner, in the above described designing method, since not only can a memory capacity of a semiconductor memory freely be changed by adjusting the number of memory segments but there is no needs for full designing including initial stages for all memory segments, reduction in a turn around time (TAT) and lower cost, as well, can be achieved as compared with a designing method in which designing is performed from its very start for each of all circuits according to a memory capacity of a semiconductor memory.
A semiconductor memory is generally provided with a redundancy circuitry used as substitution in order to improve a production yield, wherein a memory cell having a defect (defective cell) is replaced with a spare memory cell (spare cell).
A redundancy circuitry comprises a redundancy memory (for example, a fuse element) and a redundancy memory decoder, and a redundancy memory is provided, for example, in correspondence to a memory segment. In a memory segment, there is provided a spare cell array and in a redundancy memory, there is stored data for substituting a spare cell for a defective cell in a memory segment corresponding to the redundancy memory and reading out. The redundancy memory decoder has the same structure as a block decoder provided in a memory segment. The block decoder selects a memory segment and a redundancy memory decoder selects a redundancy memory corresponding to the selected memory segment.
In the above described designing method using a memory segment, however, this redundancy circuitry is also designed in advance of need singly or together with another circuit as a block. In this case, if a memory capacity of a semiconductor memory, that is the number of memory segments, is changed, not only is a structure of a block decoder in a memory segment changed but also a structure of a redundancy circuitry (a redundancy memory, a redundancy memory decoder, a switching circuit and the like) is greatly changed. Accordingly, it takes a lot of time for a change in design of the redundancy circuitry, which makes it harder designing in a short time period and with a low cost.